Image-processing method and image processor

ABSTRACT

Image data is separated from three lines of image data in accordance with the storage capacity of the source memory. The separated image data is transferred to a source memory. Several pieces of image data are read out in sequence from the transferred image data and forwarded to filtering process. The above steps are repeated to provide a line of filtered image data.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an image-processing method andimage processor for filtering image data to operatively removeencoding-caused noises.

[0003] 2. Description of the Related Art

[0004] Encoded and decoded images over a videophone and a TV conferencehave heretofore been used to provide a reduced amount of imageinformation in order to achieve efficient image transmission.

[0005] A majority of such an image encoding-decoding method in recentyears uses discrete cosine transform.

[0006] The discrete cosine transform achieves a substantial reduction inimage information amount. At the same time, the discrete cosinetransform brings up a problem of peculiar Gaussian noise called amosquito noise. The noise appears on a decoded image, and spoilssubjective image quality.

[0007] The Gaussian noise as represented by the mosquito noise isremovable using a spatial filter. The spatial filter functions to removehigh-frequency components.

[0008] The following specifically discusses filtering, in which imagedata having a QCIF (quarter common intermediate format) size (144 linesby 176 pixels) is filtered as an illustration. Each gang ofthree-pixels-by-three-pixels image data is filtered. A pixel located atthe center of three pixels-by-three pixels has target image data subjectto filtering.

[0009]FIG. 25 is a block diagram illustrating a prior art imageprocessor designed to filter target image data subject to filtering.

[0010] As shown in FIG. 25, the prior art image processor includes aprocessor 500, an image memory 501, line buffers 502 and 504, and afiltering circuit 503.

[0011] The processor 500 includes a source memory 505 and a destinationmemory 506.

[0012] The processor 500 reads out encoded image data from the imagememory 501 and writes the same encoded image data into the source memory505.

[0013] The processor 500 decodes the encoded image data in the sourcememory 505.

[0014] The processor 500 at first stores the decoded image data into thedestination memory 506, and then transfers the same image data to theimage memory 501.

[0015] The decoded image data in the image memory 501 are filtered.

[0016] In order to filter the decoded image data, 3-lines-by-176-pixelsimage data are transmitted to the line buffer 502 from the image memory501.

[0017] The line buffer 502 stores the transmitted 3-lines-by-176-pixelsimage data.

[0018] The filtering circuit 503 reads out the three pixels-by-threepixels image data from the line buffer 502 to filter a piece of targetimage data subject to filtering.

[0019] The filtering circuit 503 repeats the above steps, therebyfiltering 174-pieces of target image data subject to filtering that arestored in the line buffer 502.

[0020] Image data located in a central line of 3-lines-by-176-pixels(except for image data at opposite ends of the central line) among the3-lines-by-176-pixels image data in the line buffer 502 are target imagedata subject to filtering.

[0021] The filtering circuit 503 feeds the filtered 174-pieces of imagedata into the line buffer 504.

[0022] At the same time, the filtering circuit 503 feeds the image dataat opposite ends of the central line as previously discussed into theline buffer 504 without filtering them.

[0023] As a result, the line buffer 504 stores a line (176-pieces) offiltered image data.

[0024] As discussed above, the past practice is to transmit the imagedata to the line buffer 502 for each gang of 3-lines-by-176-pixels,thereby filtering the QCIF-sized image data.

[0025] Details of the filtering are now discussed.

[0026]FIG. 26 is a block diagram illustrating the filtering circuit 503as shown in FIG. 25. FIG. 26 illustrates the same reference characterson the same components as those shown in FIG. 25.

[0027] As shown in FIG. 26, the filtering circuit 503 includes a datareadout unit 507, a filtering unit 508, and a data write unit 509.

[0028] As shown in FIG. 26, assume that the line buffer 502 is designedto store the 3-lines-by-176-pixels image data at maximum.

[0029] The data readout unit 507 reads out image data from the linebuffer 502.

[0030] The filtering unit 508 filters the read image data.

[0031] The data write unit 509 writes the filtered image data to theline buffer 504.

[0032] The line buffer 504 is constructed to store a line (176-pixels)of image data at maximum.

[0033] The prior art image processor repeats the following steps: thedata readout unit 507 reads out three-pixels-by-three-pixels image datafrom the line buffer 502; the filtering unit 508 filters the read threepixels-by-three pixels image data; and the data write unit 509 writes apixel to the line buffer 504.

[0034] The following discusses the filtering with reference to aspecific example.

[0035]FIG. 27 is a descriptive illustration showing how image data in“N”-line of a QCIF image are filtered in a conventional manner.

[0036]FIG. 28 is a descriptive illustration showing how image data in“N+1”-line of the QCIF image are filtered in a conventional manner.

[0037] As shown in FIG. 27, the data readout unit 507 reads outthree-pixels-by-three-pixels image data 600 to perform the firstfiltering.

[0038] The filtering unit 508 filters image data (N, 2) usingsurrounding image data (N−1, 1), (N, 1) (N+1, 1), (N−1, 2), (N+1, 2),(N−1, 3), (N, 3) and (N+1, 3).

[0039] The data write unit 509 writes the filtered image data (FN, 2) tothe line buffer 504.

[0040] The data readout unit 507 reads out three-pixels-by-three-pixelsimage data 601 to execute the second filtering.

[0041] The filtering unit 508 filters image data (N, 3) usingsurrounding image data (N−1, 2), (N, 2) (N+1, 2), (N−1, 3), (N+1, 3),(N−1, 4), (N, 4) and (N+1, 4).

[0042] The data write unit 509 writes the filtered image data (FN, 3) tothe line buffer 504.

[0043] The above steps are repeated 174-times. As a result, the linebuffer 504 stores “N”-line of image data (N, 1), (FN, 2) to (FN, 175),and (N, 176).

[0044] Upon completion of the filtering of the image data in “N”-line,image data in “N+1”-line are filtered, as shown in FIG. 28.

[0045] Deleting “N−1”-line, “N+2”-line is added as the last line.

[0046] In this way, lines to be filtered are selected in sequence torepeat the above steps.

[0047] In general, pixels at both ends of the central line wheresurrounding pixels are absent are not filtered. In addition, pixels inthe first line as well as the 144th line are not filtered.

[0048] Accordingly, 142-lines-by-174-pixels image data are filtered.This means that separate steps must be taken to decode the QCIF image.

[0049] As previously discussed, filtering the image data using the priorart image processor requires one line buffer (the line buffer 502according to the above example) adapted for plural lines (three linesaccording to the above example) and another line buffer (the line buffer504 according to the above example) designed to store a line of filteredimage data, in accordance with the number of pixels to be filtered at atime (three pixels-by-three pixels according to the above example). Fordetails, refer to the published Japanese Patent Application Laid-OpenNo. 2000-251065.

[0050] Such a requirement causes a problem of an area increase in animage processor.

[0051] Another problem is that the image data are filtered in a lengthytime because each gang of three-pixels-by-three-pixels image data isread out, for each time of the filtering, from the line buffer 502 torepeat the above steps. For details, refer to the published JapanesePatent Application Laid-Open No. 7-111586.

[0052] Furthermore, in order to process edgewise pixels, only apredetermined number of pixels are processed.

[0053] This causes a further problem that a change in image sizeprecludes the filtering of the image data.

OBJECTS AND SUMMARY OF THE INVENTION

[0054] In view of the above, an object of the present invention is toprovide an image processor and image-processing method for inhibiting anarea increase in an image processor, processing image data in a reducedtime, and coping with a change in image size.

[0055] A first aspect of the present invention provides animage-processing method comprising: transferring image data to a storageunit, the image data being formed by several pieces of image data, theimage data being separated from several lines of image data;sequentially reading out the several pieces of image data from thestorage unit; and filtering target image data subject to filtering usingpredetermined pieces of the read image data.

[0056] The above method allows several lines of image data to be dividedinto partitions in accordance with the storage capacity of a destinationor rather the storage unit in order to transfer the partitions to thestorage unit. This feature eliminates a storage unit having largestorage capacity sufficient to store the several lines of image data.Consequently, an area increase in an image processor is inhibited.

[0057] The above method allows an existing storage unit to be used as adestination. This feature eliminates a dedicated storage unit designedfor filtering, which serves as a destination. Consequently, an areaincrease in an image processor is again inhibited.

[0058] The above method sequentially reads out several pieces of imagedata from the storage unit. This feature filters several pieces oftarget image data subject to filtering without reading out the sameimage data several times. As a result, the target image data subject tofiltering can be filtered in a reduced time.

[0059] The above method makes it feasible to filter the target imagedata subject to filtering without fixing the number of pixels in a line.This feature filters the target image data subject to filteringindependently of an image size.

[0060] A second aspect of the present invention is to provide animage-processing method comprising: sequentially entering several piecesof image data that are used to filter several pieces of target imagedata subject to filtering; shifting the sequentially entered severalpieces of image data; parallel-feeding predetermined pieces of theshifted image data; and filtering the target image data subject tofiltering using the parallel-fed predetermined pieces of the shiftedimage data.

[0061] The above method sequentially reads out several pieces of imagedata from the storage unit for use in filtering several pieces of targetimage data subject to filtering. This feature filters the several piecesof target image data subject to filtering without reading out the sameimage data several times. As a result, the target image data subject tofiltering can be filtered in a shorter time.

[0062] A third aspect of the present invention is to provide an imageprocessor comprising: a first storage unit operable to store image dataformed by several pieces of image data, the image data being separatedfrom several lines of image data; a data readout unit operable tosequentially read out the several pieces of image data stored by thefirst storage unit; a filtering unit operable to filter target imagedata subject to filtering using predetermined pieces of the image dataread out from the data readout unit; a second storage unit operable tostore the filtered target image data subject to filtering; and a datawrite unit operable to write the filtered target image data subject tofiltering to the second storage unit.

[0063] The above image processor allows several lines of image data tobe divided into partitions in accordance with the storage capacity of adestination or rather the first storage unit in order to transfer thepartitions to the first storage unit. This feature eliminates a firststorage unit having large storage capacity sufficient to store theseveral lines of image data.

[0064] The above image processor allows an existing storage unit to beused as a destination or rather the first storage unit. This featureeliminates a dedicated first storage unit designed for filtering, whichserves as a destination.

[0065] The above image processor filters several pieces of target imagedata subject to filtering, which are included in image data separatedfrom several lines of image data. This feature eliminates the need toprovide a second storage unit having large storage capacity sufficientto store a line of image data.

[0066] The above image processor allows an existing storage unit to beused as the second storage unit where the image data are written. Thisfeature eliminates the need to provide a dedicated second storage unitdesigned for filtering, to which the image data are written.

[0067] Consequently, the above features inhibit an area increase in animage processor.

[0068] The above image processor sequentially reads out several piecesof image data from the first storage unit. This feature filters severalpieces of target image data subject to filtering without reading out thesame image data several times. As a result, the target image datasubject to filtering can be filtered in a reduced time.

[0069] The above image processor makes it feasible to filter the targetimage data subject to filtering without providing a fixed number ofpixels in a line. This feature filters the target image data subject tofiltering independently of an image size.

[0070] A fourth aspect of the present invention is to provide an imageprocessor as defined in the third aspect of the present invention,wherein the filtering unit comprises a data output control unit operableto feed filtered target image data subject to filtering, but operablenot to feed a predetermined piece of non-filtered image data inaccordance with mode information.

[0071] According to the above image processor, the data output controlunit removes unnecessary image data produced in the course of filteringthe target image data subject to filtering. As a result, only therequired image data are provided. This feature produces line data in areduced time.

[0072] A fifth aspect of the present invention is to provide an imageprocessor as defined in the third aspect of the present invention,wherein the filtering unit comprises a data output control unit operableto practice a countdown from an initial value each time when the imagedata is fed, the initial value being determined in accordance with thenumber of pixels to be processed, the data output control unit beingoperable to feed only a predetermined piece of non-filtered image dataas well as filtered target image data subject to filtering in accordancewith results from the countdown.

[0073] According to the above image processor, the data output controlunit removes unnecessary image data produced in the course of filteringthe target image data subject to filtering. As a result, only therequired image data are provided. This feature produces line data in areduced time.

[0074] The above image processor initially sets up the number of pixelsto be processed. Such a simple setup provides subsequent edgewise pixelprocessing. This feature allows edgewise pixel-processing information tobe set up a smaller number of times.

[0075] A sixth aspect of the present invention is to provide an imageprocessor as defined in the third aspect of the present invention,wherein the filtering unit comprises a image data-retaining unitoperable to retain several pieces of image data for use at the time ofthe next filtering, the several pieces of image data for use at the timeof the next filtering being selected from among several pieces of imagedata read out by the data readout unit from the first storage unit.

[0076] At the end of the present filtering, the above image processorretains image data required for the following filtering, thereby usingthe retained image data at the time of the following filtering. Thisfeature allows the data to be transferred a smaller number of times.

[0077] Embodiments of the present invention exemplify a QCIF (quartercommon intermediate format) size in which image data to be filteredconsists of 144-lines-by-176-pixels.

[0078] In the 144-lines-by-176 pixels QCIF size, linearly aligned176-pixels forms a line; and a plurality of the lines are arranged inparallel to form 144-lines, thereby providing an image plane.

[0079] The above, and other objects, features and advantages of thepresent invention will become apparent from the following descriptionread in conjunction with the accompanying drawings, in which likereference numerals designate the same elements.

BRIEF DESCRIPTION OF THE DRAWINGS

[0080]FIG. 1 is a block diagram illustrating an image processoraccording to a first embodiment of the present invention;

[0081]FIG. 2 is a schematic illustration showing how the image processoraccording to the first embodiment filters image data;

[0082]FIG. 3(a) is an illustration showing a flow of the first filteringprovided by the image processor according to the first embodiment;

[0083]FIG. 3(b) is an illustration showing a flow of the secondfiltering provided by the image processor according to the firstembodiment;

[0084]FIG. 3(c) is an illustration showing a flow of the third filteringprovided by the image processor according to the first embodiment;

[0085]FIG. 4 is a block diagram illustrating a filtering circuit of theimage processor according to the first embodiment;

[0086] FIGS. 5(a), 5(b), and 5(c) are descriptive illustration showingthe first filtering provided by the image processor according to thefirst embodiment;

[0087] FIGS. 6(a), 6(b), and 6(c) are descriptive illustration showingthe second filtering provided by the image processor according to thefirst embodiment;

[0088] FIGS. 7(a), 7(b), and 7(c) are descriptive illustration showingthe third filtering provided by the image processor according to thethird embodiment;

[0089]FIG. 8(a) is an illustration showing a flow of the first filteringprovided by an image processor according to a second embodiment;

[0090]FIG. 8(b) is an illustration showing a flow of the secondfiltering provided by the image processor according to the secondembodiment;

[0091]FIG. 8(c) is an illustration showing a flow of the third filteringprovided by the image processor according to the second embodiment;

[0092]FIG. 9 is a block diagram illustrating a filtering circuit of theimage processor according to the second embodiment;

[0093] FIGS. 10(a), 10(b), 10(c), 10(d), and 10(e) are descriptiveillustrations showing the first filtering provided by the imageprocessor according to the second embodiment;

[0094] FIGS. 11(a), 11(b), 11(c), 11(d), and 11(e) are descriptiveillustrations showing the first filtering provided by the imageprocessor according to the second embodiment;

[0095] FIGS. 12(a), 12(b), 12(c), 12(d), and 12(e) are descriptiveillustrations showing the third filtering provided by the imageprocessor according to the second embodiment;

[0096]FIG. 13(a) is a descriptive illustration showing mode information2′b 00 in the image processor according to the second embodiment;

[0097]FIG. 13(b) is a descriptive illustration showing mode information2′b 01 in the image processor according to the second embodiment;

[0098]FIG. 13(c) is a descriptive illustration showing mode information2′b 10 in the image processor according to the second embodiment;

[0099]FIG. 13(d) is a descriptive illustration showing mode information2′b 11 in the image processor according to the second embodiment;

[0100]FIG. 14(a) is a descriptive illustration showing the usage of modeinformation 2′b 01 in the image processor according to the secondembodiment;

[0101]FIG. 14(b) is a descriptive illustration showing the usage of modeinformation 2′b 11 in the image processor according to the secondembodiment;

[0102]FIG. 14(c) is a descriptive illustration showing the usage of modeinformation 2′b 10 in the image processor according to the secondembodiment;

[0103]FIG. 15 is a block diagram illustrating a filtering circuit of animage processor according to a third embodiment;

[0104]FIG. 16 is a schematic illustration showing how the imageprocessor according to the third embodiment filters image data;

[0105]FIG. 17(a) is an illustration showing a flow of the firstfiltering provided by the image processor according to the thirdembodiment;

[0106]FIG. 17(b) is an illustration showing a flow of the secondfiltering provided by the image processor according to the thirdembodiment;

[0107]FIG. 17(c) is an illustration showing a flow of the thirdfiltering provided by the image processor according to the thirdembodiment;

[0108] FIGS. 18(a), 18(b), and 18(c) are descriptive illustrationsshowing characteristics of filtering steps taken by the image processoraccording to the third embodiment;

[0109]FIG. 19 is a block diagram illustrating a filtering circuit of animage processor according to a fourth embodiment;

[0110]FIG. 20 is a schematic illustration showing how the imageprocessor according to the fourth embodiment filters image data;

[0111]FIG. 21(a) is an illustration showing a flow of the firstfiltering provided by the image processor according to the fourthembodiment;

[0112]FIG. 21(b) is an illustration showing a flow of the secondfiltering provided by the image processor according to the fourthembodiment;

[0113]FIG. 21(c) is an illustration showing a flow of the thirdfiltering provided by the image processor according to the fourthembodiment;

[0114] FIGS. 22(a), 22(b), 22(c), 22(d), and 22(e) are descriptiveillustrations showing the first filtering provided by the imageprocessor according to the fourth embodiment;

[0115] FIGS. 23(a), 23(b), 23(c), 23(d), 23(e), and 23(f) aredescriptive illustrations showing the second filtering provided by theimage processor according to the fourth embodiment;

[0116] FIGS. 24(a), 24(b), 24(c), 24(d), 24(e), and 24(f) aredescriptive illustrations showing the third filtering provided by theimage processor according to the fourth embodiment;

[0117]FIG. 25 is a block diagram illustrating a prior art imageprocessor;

[0118]FIG. 26 is a block diagram illustrating a filtering circuit of theprior art image processor;

[0119]FIG. 27 is a descriptive illustration showing how the prior artimage processor filters “N”-line of target pixels subject to filtering;and,

[0120]FIG. 28 is a descriptive illustration showing how the prior artimage processor filters “N+1”-line of target pixels subject tofiltering.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0121] Embodiments of the present invention are discussed in accordancewith the accompanying drawings.

[0122] (First Embodiment)

[0123]FIG. 1 is a block diagram illustrating an image processoraccording to a first embodiment.

[0124] As illustrated in FIG. 1, the image processor includes aprocessor 1, an image memory 2, and a filtering circuit 3.

[0125] The processor 1 includes a source memory 10, a destination memory11, and a control unit 12.

[0126] Next, the entire behavior of the image processor is brieflydiscussed.

[0127] The processor 1 reads out encoded image data from the imagememory 2 and writes the same encoded image data into the source memory10.

[0128] The processor 1 decodes the encoded image data in the sourcememory 10.

[0129] The processor 1 at first places the decoded image data into thedestination memory 11, and then transfers the same image data to theimage memory 2 from the destination memory 11.

[0130] The decoded image data transferred to the image memory 2 isfiltered.

[0131] In order to filter the decoded image data, 3-lines-by-176-pixelsimage data are divided into partitions in accordance with the storagecapacity of the source memory 10. The divided image data are transmittedto the source memory 10.

[0132] The control unit 12 reads out the divided image data from thesource memory 10, and then transmits the same image data to thefiltering circuit 3.

[0133] The filtering circuit 3 filters the divided image data to removenoises.

[0134] The control unit 12 writes the divided image data free of thenoises to the destination memory 11, and further to the image memory 2.

[0135] The above steps are repeated to remove the noises from QCIF-sizedimage data.

[0136] An image output circuit (not shown) feeds the image data free ofthe noises into a display device (not shown) from the image memory 2. Asa result, the image data free of the noises are displayed on the displaydevice (not shown). The display device is, e.g., an LCD (liquid crystaldisplay).

[0137] Next, the filtering is briefly discussed.

[0138]FIG. 2 is a schematic diagram illustrating how the image processoraccording to the present embodiment filters the image data.

[0139] Assume that the image memory 2 of FIG. 1 stores the decoded,QCIF-sized image data.

[0140] For convenience of description, FIG. 2 illustrates3-lines-by-176-pixels image data 100 among the QCIF-sized image datastored in the image memory 2.

[0141] In FIG. 2, each piece of image data is illustrated in circle. Acircle filled with slant lines denotes image data to be filtered(hereinafter called “target image data subject to filtering”). A blackedout circle denotes filtered target image data subject to filtering(hereinafter simply called “filtered image data”).

[0142] In FIG. 2, the source memory 10 of FIG. 1 has a storage capacitysufficient to store three-pixels-by-six-pixels image data at maximum.

[0143] Each gang of three-pixels-by-three-pixels image data is filtered.A pixel located at the center of three pixels-by-three pixels has targetimage data subject to filtering.

[0144] As illustrated in FIG. 2, three-pixels-by-five-pixels image data101 divided from the 3-lines-by-176-pixels image data 100 is at firsttransferred to the source memory 10 from the image memory 2.

[0145] The image data 101 is sent, for each piece of image data, fromthe source memory 10 to the filtering circuit 3.

[0146] The filtering circuit 3 filters a piece of target image datasubject to filtering using the given three-pixels-by-three-pixels imagedata.

[0147] In this way, all three pieces of target image data subject tofiltering in the image data 101 are filtered.

[0148] Three-pixels-by-six-pixels image data 102 divided from the3-lines-by-176-pixels image data 100 is transferred to the source memory10 from the image memory 2.

[0149] The image data 102 is sent, for each piece of image data, fromthe source memory 10 to the filtering circuit 3.

[0150] The filtering circuit 3 filters a piece of target image datasubject to filtering using the given three-pixels-by-three-pixels imagedata.

[0151] In this way, all four pieces of target image data subject tofiltering in the image data 102 are filtered.

[0152] The above steps are repeated to filter all target image datasubject to filtering in the 3-lines-by-176-pixels image data 100.

[0153] As a result, a line of filtered image data 105 is obtained.

[0154] In the image data 100, image data in a second line at the bothends thereof are not filtered.

[0155] Details of the filtering are now discussed with reference toFIGS. 1, 3, 4, 5, 6, and 7, in which the source memory 10 is designed tostore 3-lines-by-64-pixels image data at maximum.

[0156] Each gang of three-pixels-by-three-pixels image data is filtered.A pixel located at the center of three pixels-by-three pixels has targetimage data subject to filtering.

[0157] FIGS. 3(a), 3(b), and 3(c) are illustrations showing a flow offiltering steps. FIG. 3(a) is an illustration showing a flow of firstfiltering. FIG. 3(b) is an illustration showing a flow of secondfiltering. FIG. 3(c) is an illustration showing a flow of thirdfiltering. FIG. 3 illustrates the same reference characters on the samecomponents as those described in FIG. 1.

[0158]FIG. 4 is a block diagram illustrating the filtering circuit 3 ofFIG. 1. As illustrated in FIG. 4, the filtering circuit 3 includes ashift register 30 and a filter calculator 31. The shift register 30includes nine flip-flops FF1 to FF9.

[0159] The filter calculator 31 sometimes feeds image data designated bysign “#”. The filter calculator 31 feeds unfiltered image data as wellas filtered image data. The unfiltered image data is discussed later.

[0160]FIG. 5(a), 5(b), and 5(c) are time charts showing the firstfiltering. FIG. 5(a) is an illustration showing, for each cycle, imagedata sent to the filter calculator 31 of FIG. 4. FIG. 5(b) is anillustration showing filtered image data fed from the filter calculator31. FIG. 5(c) is an illustrating showing an effective data-indicatingsignal fed from the filter calculator 31.

[0161]FIG. 6(a), 6(b), and 6(c) are time charts showing the secondfiltering. FIG. 6(a) is an illustration showing, for each cycle, imagedata sent to the filter calculator 31. FIG. 6(b) is an illustrationshowing filtered image data fed from the filter calculator 31. FIG. 6(c)is an illustrating showing an effective data-indicating signal fed fromthe filter calculator 31.

[0162]FIG. 7(a), 7(b), and 7(c) are time charts showing the thirdfiltering. FIG. 7(a) is an illustration showing, for each cycle, imagedata sent to the filter calculator 31. FIG. 7(b) is an illustrationshowing filtered image data fed from the filter calculator 31. FIG. 7(c)is an illustrating showing an effective data-indicating signal fed fromthe filter calculator 31.

[0163] The following discusses details of the first filtering withreference to FIG. 3(a), FIG. 4, and FIG. 5. The first filtering refersto filtering using image data that covers from the first pixel to thesixty-fourth pixel. These pixels are separated from the3-lines-by-176-pixels image data among the QCIF-sized image data.

[0164] As illustrated in FIG. 3(a), the image memory 2 of FIG. 1transmits 3-pixels-by-64-pixels image data to the source memory 10, inwhich the transmitted 3-pixels-by-64-pixels image data are stored.

[0165] The stored image data is obtained by dividing the3-lines-by-176-pixels image data among the QCIF-sized image data in theimage memory 2 in accordance with the storage capacity of the sourcememory 10.

[0166] The stored image data consists of 192-pieces of image data:(N−1, 1) to (N−1, 64); (N, 1) to (N, 64); and (N+1, 1) to (N+1, 64).

[0167] The above image data includes target image data subject tofiltering as illustrated by (N, 2) to (N, 63).

[0168] For convenience of description, the image data from (N−1, 1) to(N+1, 64) in the source memory 10 are sometimes designated as image data“D”.

[0169] The data readout unit 120 reads out 3-pixels-by-64-pixels imagedata from the source memory 10. More specifically, the image data areread out up to (N−1, 64), (N, 64), and (N+1, 64) in the order of (N−1,1), (N, 1), (N+1, 1), (N−1, 2), (N, 2), (N+1, 2), (N−1, 3), (N, 3),(N+1, 3), (N−1, 4), (N, 4), (N+1, 4), and so on.

[0170] The data readout unit 120 feeds the read image data “D” insequence into the filtering circuit 3.

[0171] Pursuant to the present embodiment, the control unit 12 of FIG. 1functions as the data readout unit 120.

[0172] The filtering circuit 3 in receipt of filtering start signal “Ss”from the data readout unit 120 sequentially receives image data “D” fromthe source memory 10. Filtering start signal “Ss” directs the filteringcircuit 3 to start the filtering.

[0173] As illustrated in FIG. 4, the shift register 30 sequentiallyreceives image data “D”. The shift register 30 provides a shift actionin accordance with clock “CLK”.

[0174] Flip-flops “FF1” to “FF9” feed the retained image data “D1” to“D9” in parallel into the filter calculator 31.

[0175] The filter calculator 31 filters the target image data subject tofiltering using the nine pieces of image data “D1” to “D9”, therebyproviding a piece of filtered image data D# as a result of thefiltering.

[0176] Image data “D” from the source memory 10 sequentially enters theshift register 30. As a result, all of the target image data subject tofiltering included in the image data in the source memory 10 arefiltered, thereby providing filtered image data “D#”.

[0177] The data write unit 121 of FIG. 3(a) sequentially writes filteredimage data D# to the destination memory 11 of FIG. 1 in accordance witheffective data-indicating signal “SE” from the filter calculator 31.

[0178] According to the present embodiment, the control unit 12 of FIG.1 functions as the data write unit 121.

[0179] The following discusses further specific steps taken by thefiltering circuit 3.

[0180] As illustrated in FIG. 5(a), at cycle “CY1”, the shift register30 feeds nine pieces of serially aligned image data (N−1, 1) to (N+1, 3)into the filter calculator 31 in parallel.

[0181] The filter calculator 31 filters target image data subject tofiltering (N, 2) using the nine pieces of image data (N−1, 1) to (N+1,3), thereby providing filtered image data (FN, 2) as shown in FIG. 5(b).

[0182] As illustrated in FIG. 5(c), the data write unit 121 writesfiltered image data (FN, 2) to the destination memory 11 in accordancewith effective data-indicating signal “SE” from the filter calculator31.

[0183] The data write unit 121 performs the writing when effectivedata-indicating signal “SE” is at the level of “H (high)”.

[0184] As shown in FIG. 5(a), at the next cycle “CY2”, the shiftregister 30 feeds nine pieces of image data (N, 1) to (N−1, 4) inparallel.

[0185] At the following cycle “CY3”, the shift register 30 feeds ninepieces of image data (N+1, 1) to (N, 4) in parallel.

[0186] At cycle “CY4”, the shift register 30 feeds nine pieces of imagedata (N−1, 2) to (N+1, 4) in parallel.

[0187] The filter calculator 31 filters target image data subject tofiltering (N, 3) using nine pieces of image data (N−1, 2) to (N+1, 4),thereby providing filtered image data (FN, 3) as shown in FIG. 5(b).

[0188] As illustrated FIG. 5(c), the data write unit 121 writes filteredimage data (FN, 3) to the destination memory 11 in accordance witheffective data-indicating signal “SE” from the filter calculator 31.

[0189] The above steps are repeated until filtering end signal “Se”enters the filtering circuit 3 from the data readout unit 120.

[0190] More specifically, as shown in FIG. 5(a), the filtering circuit 3repeats the filtering sixty-two times (where each time constists ofthree cycles), thereby providing sixty-two pieces of filtered image data(FN, 2) to (FN, 63). As a result, the destination memory 11 storesfiltered image data (FN, 2) to (FN, 63).

[0191] As illustrated in FIG. 5(b), the filter calculator 31 feeds andnon-filters two pieces of image data (N, 1) and (N, 64) among the imagedata in the source memory 10 of FIG. 3(a). Image data (N, 1) and (N, 64)are located in the central line of the image data in the source memory10 at both ends of the central line.

[0192] The data write unit 121 writes the non-filtered image data (N,1), (N, 64) to the destination memory 11 in accordance with effectivedata-indication signal “SE” as shown in FIG. 5(c).

[0193] As a result, as illustrated FIG. 3(a), the destination memory 11stores the filtered image data (FN, 2) to (FN, 63) and the non-filteredimage data (N, 1), (N, 64).

[0194] The image data consisting of (FN, 2) to (FN, 63), (N, 1), and (N,64) as just discussed are transmitted to the image memory 2.

[0195] The following discusses details of the second filtering withreference to FIG. 3(b), FIG. 4, and FIG. 6. The second filtering refersto filtering using image data that covers from the sixty-third pixel tothe one hundred and twenty-sixth pixel. These pixels are separated fromthe 3-lines-by-176-pixels image data among the QCIF-sized image data.

[0196] As illustrated in FIG. 3(b), the image memory 2 of FIG. 1transmits 3-pixels-by-64-pixels image data to the source memory 10, inwhich the transmitted 3-pixels-by-64-pixels image data is stored.

[0197] The stored image data is obtained by dividing the3-lines-by-176-pixels image data among the QCIF-sized image data in theimage memory 2 in accordance with the storage capacity of the sourcememory 10.

[0198] The stored image data consists of 192-pieces of image data: (N−1,63) to (N−1, 126); (N, 63) to (N, 126); (N+1, 63) to (N+1, 126).

[0199] The above image data includes target image data subject tofiltering (N, 64) to (N, 125).

[0200] For convenience of description, the image data of (N−1, 63) to(N+1, 126) in the source memory 10 are sometimes designated as imagedata “D”.

[0201] The data readout unit 120 reads out 3-pixels-by-64-pixels imagedata from the source memory 10. More specifically, the image data areread out up to (N−1, 126), (N, 126), and (N+1, 126) in the order of(N−1, 63), (N, 63), (N+1, 63), (N−1, 64), (N, 64), (N+1, 64), (N−1, 65),(N, 65), (N+1, 65), (N−1, 66), (N, 66), (N+1, 66), and so on.

[0202] The data readout unit 120 feeds the read image data (N−1, 63)etc. in sequence into the filtering circuit 3.

[0203] As illustrated in FIG. 6(a), at cycle “CY1”, the shift register30 feeds nine pieces of serially aligned image data (N−1, 63) to (N+1,65) into the filter calculator 31 in parallel.

[0204] The filter calculator 31 filters target image data subject tofiltering (N, 64) using the nine pieces of image data (N−1, 63) to (N+1,65), thereby providing filtered image data (FN, 64) as shown in FIG.6(b).

[0205] As illustrated in FIG. 6(c), the data write unit 121 writes thefiltered image data (FN, 64) to the destination memory 11 in accordancewith effective data-indicating signal “SE” from the filter calculator31.

[0206] As shown in FIG. 6(a), at the next cycle “CY2”, the shiftregister 30 feeds nine pieces of image data (N, 63) to (N−1, 66) inparallel.

[0207] At the following cycle “CY3”, the shift register 30 feeds ninepieces of image data (N+1, 63) to (N, 66) in parallel.

[0208] At cycle “CY4”, the shift register 30 feeds nine pieces of imagedata (N−1, 64) to (N+1, 66) in parallel.

[0209] The filter calculator 31 filters target image data subject tofiltering (N, 65) using the nine pieces of image data (N−1, 64) to (N+1,66), thereby providing filtered image data (FN, 65) as shown in FIG.6(b).

[0210] As illustrated FIG. 6(c), the data write unit 121 writes filteredimage data (FN, 65) to the destination memory 11 in accordance witheffective data-indicating signal “SE” from the filter calculator 31.

[0211] The above steps are repeated until filtering end signal “Se”enters the filtering circuit 3 from the data readout unit 120.

[0212] More specifically, as shown in FIG. 6(a), the filtering circuit 3repeats the filtering sixty-two times (where each time constists ofthree cycles), thereby providing sixty-two pieces of filtered image data(FN, 64) to (FN, 125). As a result, the destination memory 11 storesfiltered image data (FN, 64) to (FN, 125).

[0213] As shown in FIG. 6(b), the filter calculator 31 feeds andnon-filters two pieces of image data (N, 63) and (N, 126) among theimage data in the source memory 10 of FIG. 3(a). Image data (N, 63), (N,126) are located in the central line of the image data in the sourcememory 10 at both ends of the central line.

[0214] The data write unit 121 writes the non-filtered image data (N,63), (N, 126) to the destination memory 11 in accordance with effectivedata-indication signal “SE” as shown in FIG. 6(c).

[0215] As a result, as illustrated FIG. 3(b), the destination memory 11stores the filtered image data (FN, 64) to (FN, 125) and thenon-filtered image data (N, 63), (N, 126).

[0216] The image data of (FN, 64) to (FN, 125), (N, 63), and (N, 126) asdiscussed above are transmitted to the image memory 2.

[0217] The following discusses details of the third filtering withreference to FIG. 3(c), FIG. 4, and FIG. 7. The third filtering refer tofiltering using image data that covers from the one hundred andtwenty-fifth pixel to the one hundred and seventy-sixth pixel. Thesepixels are separated from the 3-lines-by-176-pixels image data among theQCIF-sized image data.

[0218] As illustrated in FIG. 3(c), the image memory 2 of FIG. 1transmits 3-pixels-by-52-pixels image data to the source memory 10, inwhich the transmitted 3-pixels-by-52-pixels image data are stored.

[0219] The stored image data is obtained by dividing the3-lines-by-176-pixels image data among the QCIF-sized image data in theimage memory 2 in accordance with the storage capacity of the sourcememory 10.

[0220] The stored image data consists of 156-pieces of image data: (N−1,125) to (N−1, 176); (N, 125) to (N, 176); (N+1, 125) to (N+1, 176).

[0221] The above image data includes target image data subject tofiltering (N, 126) to (N, 175).

[0222] For convenience of description, the image data of (N−1, 125) to(N+1, 176) in the source memory 10 are sometimes designated as imagedata “D”.

[0223] The data readout unit 120 reads out 3-pixels-by-52-pixels imagedata from the source memory 10. More specifically, the image data areread out up to (N−1, 176), (N, 176), and (N+1, 176) in the order of(N−1, 125), (N, 125), (N+1, 125), (N−1, 126), (N, 126), (N+1, 126),(N−1, 127), (N, 127), (N+1, 127), (N−1, 128), (N, 128), (N+1, 128), andso on.

[0224] The data readout unit 120 feeds the read image data (N−1, 125)etc. in sequence into the filtering circuit 3.

[0225] As illustrated in FIG. 7(a), at cycle “CY1”, the shift register30 feeds nine pieces of serially aligned image data (N−1, 125) to (N+1,127) into the filter calculator 31 in parallel.

[0226] The filter calculator 31 filters target image data subject tofiltering (N, 126) using nine pieces of image data (N−1, 125) to (N+1,127), thereby providing filtered image data (FN, 126) as shown in FIG.7(b).

[0227] As illustrated in FIG. 7(c), the data write unit 121 writes thefiltered image data (FN, 126) to the destination memory 11 in accordancewith effective data-indicating signal “SE” from the filter calculator31.

[0228] As shown in FIG. 7(a), at the next cycle “CY2”, the shiftregister 30 feeds nine pieces of image data (N, 125) to (N−1, 128) inparallel.

[0229] At the following cycle “CY3”, the shift register 30 feeds ninepieces of image data (N+1, 125) to (N, 128) in parallel.

[0230] At cycle “CY4”, the shift register 30 feeds nine pieces of imagedata (N−1, 126) to (N+1, 128) in parallel.

[0231] The filter calculator 31 filters target image data subject tofiltering (N, 127) using the nine pieces of image data (N−1, 126) to(N+1, 128), thereby providing filtered image data (FN, 127) as shown inFIG. 7(b).

[0232] As illustrated FIG. 7(c), the data write unit 121 writes filteredimage data (FN, 127) to the destination memory 11 in accordance witheffective data-indicating signal “SE” from the filter calculator 31.

[0233] The above steps are repeated until filtering end signal “Se”enters the filtering circuit 3 from the data readout unit 120.

[0234] More specifically, as shown in FIG. 7(a), the filtering circuit 3repeats the filtering fifty times (where each time constists of threecycles), thereby providing fifty pieces of filtered image data (FN, 126)to (FN, 175). As a result, the destination memory 11 stores the filteredimage data of (FN, 126) to (FN, 175).

[0235] As illustrated in FIG. 7(b), the filter calculator 31 feeds andnon-filters two pieces of image data (N, 125) and (N, 176) among theimage data in the source memory 10. Image data (N, 125) and (N, 176) arelocated in the central line of the image data in the source memory 10 atboth ends of the central line.

[0236] The data write unit 121 writes the non-filtered image data (N,125), (N, 176) to the destination memory 11 in accordance with effectivedata-indication signal “SE” as shown in FIG. 7(c).

[0237] Consequently, as illustrated FIG. 3(c), the destination memory 11stores the filtered image data of (FN, 126) to (FN, 175) and thenon-filtered image data of (N, 125), (N, 176).

[0238] The image data of (FN, 126) to (FN, 175), (N, 125), and (N, 176)are transmitted to the image memory 2.

[0239] As a result, the image memory 2 stores: filtered image data (FN,2) to (FN, 63) and non-filtered image data (N, 1), (N, 64); filteredimage data (FN, 64) to (FN, 125) and non-filtered image data (N, 63),(N, 126); and filtered image data (FN, 126) to (FN, 175) andnon-filtered image data (N, 125), and (N, 176).

[0240] The processor 1 removes unnecessary image data (N, 64), (N, 63),(N, 126), and (N, 125), thereby forming line data that consists of imagedata from (N, 1), (FN, 2) to (FN, 175), and (N, 176).

[0241] In this way, an image output circuit (not shown) feeds asubsequently created series of line data from the image memory 2 to adisplay device (not shown), thereby displaying the line data on thedisplay device (not shown).

[0242] As described above, the image processor according to the presentembodiment divides three-lines image data into partitions in accordancewith the storage capacity of the source memory 10 to place thepartitions into the source memory 10 in order to perform filteringcalculation.

[0243] This feature eliminates a buffer for three lines (see a linebuffer 502 of FIG. 25), to which image data are transferred from theimage memory 2 to filter the image data, and a buffer for a single line(see a line buffer 504 of FIG. 25) to store filtered image data. Thismeans that a reduced area of an image processor is achievable.

[0244] A prior art image processor reads out image data for each gang ofthree pixels-by-three pixels to filter the image data (see FIGS. 27 and28). Different from the prior art image processor, the image processoraccording to the present embodiment is operable to sequentially read outseveral pieces of image data from the source memory 10. This featuremakes it feasible to filter several pieces of target image data subjectto filtering without the need to read out the same image data severaltimes. As a result, the target image data subject to filtering can befiltered in a shorter time.

[0245] The image processor according to the present embodiment isoperable to filter the target image data subject to filtering withoutproviding a fixed number of pixels in a line. This means that the targetimage data subject to filtering can be filtered independently of animage size.

[0246] The present embodiment illustrates the QCIF-sized image as atarget to be filtered. However, the present embodiment is not limitedthereto.

[0247] Assume that “p”-lines-by-“q”-pixels image data are to befiltered, and further that each gang of “P”-pixels-by-“Q”-pixels isfiltered. The “p”-lines-by-“q”-pixels image data is divided into severalpartitions in accordance with the storage capacity of the source memory10. “P”-pixels-by-“Y”-pixels image data is transmitted to the sourcememory 10. As a result, filtering calculation is achievable.

[0248] (Second Embodiment)

[0249] An image processor according to a second embodiment includes afiltering circuit 4 substituted for the filtering circuit 3 of FIG. 1.The filtering circuit 4 is discussed below. The image processoraccording to the present embodiment is similar in construction to theimage processor of FIG. 1 except for the filtering circuit justdiscussed above.

[0250] FIGS. 8(a), 8(b), and 8(c) are illustrations showing a flow offiltering steps. FIG. 8(a) is an illustration showing a flow of thefirst filtering. FIG. 8(b) is an illustration showing a flow of thesecond filtering. FIG. 8(c) is an illustration showing a flow of thethird filtering. FIG. 8 illustrates the same reference characters oncomponents similar to those shown in FIG. 1.

[0251]FIG. 9 is a block diagram illustrating the filtering circuit 4. Asshown in FIG. 9, the filtering circuit 4 includes a data output controlunit 80 other than the same components as those of the filtering circuit3 of FIG. 4.

[0252] The data output control unit 80 includes a register 33 and anedgewise pixel processor 32. The edgewise pixel processor 32 processesedgewise pixels.

[0253] The edgewise pixel processor 32 sometimes feeds image datadesignated as The edgewise pixel processor 32 feeds filtered image dataas well as non-filtered image data as discussed later.

[0254] FIGS. 10(a), 10(b), 10(c), 10(d), and 10(e) are time chartsillustrating the first filtering. FIG. 10(a) is an illustration showing,for each cycle, image data provided to a filter calculator 31 of FIG. 9.FIG. 10(b) is an illustration showing image data fed from the filtercalculator 31. FIG. 10(c) is an illustration showing an effectivedata-indicating signal from the filter calculator 31. FIG. 10(d) is anillustration showing image data written by a data write unit 121 to adestination memory 11. FIG. 10(e) is an illustration showing awrite-indicating signal from the edgewise pixel processor 32.

[0255] FIGS. 11(a), 11(b), 11(c), 11(d), and 11(e) are time chartsillustrating the second filtering. FIG. 11(a) is an illustrationshowing, for each cycle, image data sent to the filter calculator 31.FIG. 11(b) is an illustration showing image data fed from the filtercalculator 31. FIG. 11(c) is an illustration showing an effectivedata-indicating signal from the filter calculator 31. FIG. 11(d) is anillustration showing image data written by the data write unit 121 tothe destination memory 11. FIG. 11(e) is an illustration showing awrite-indicating signal from the edgewise pixel processor 32.

[0256] FIGS. 12(a), 12(b), 12(c), 12(d), and 12 (e) are time chartsillustrating the third filtering. FIG. 12(a) is an illustration showing,for each cycle, image data sent to the filter calculator 31. FIG. 12(b)is an illustration showing image data fed from the filter calculator 31.FIG. 12(c) is an illustration showing an effective data-indicatingsignal from the filter calculator 31. FIG. 12(d) is an illustrationshowing image data written by the data write unit 121 to the destinationmemory 11. FIG. 12(e) is an illustration showing a write-indicatingsignal from the edgewise pixel processor 32.

[0257] The filtering steps are now described in the order of the first,second, and third filtering, in which the source memory 10 of FIG. 1 isadapted to store 3-lines-by-64-pixels image data at maximum.

[0258] Assume that each gang of three-pixels-by-three-pixels image datais filtered, and further that a pixel located at the center of threepixels-by-three pixels has target image data subject to filtering.

[0259] The first filtering is discussed with reference to FIG. 1, FIG.8(a), FIG. 9, and FIGS. 10(a) to 10(e).

[0260] Steps taken until the filter calculator 31 of FIG. 9 feedsfiltered image data D# and effective data-indicating signal “SE” are thesame as the steps (see FIGS. 5(a) to 5(c)) taken until the filtercalculator 31 of FIG. 4 according to the previous embodiment feedsfiltered image data D# and effective data-indicating signal “SE”.Therefore, descriptions related to the above steps are omitted.

[0261] However, before starting the first filtering, mode signal “SM”sets mode information “M” into the register 33 of FIG. 9. Modeinformation “M” prohibits feeding a rightmost piece of image data.Details of this step are discussed later.

[0262] As illustrated in FIG. 10(b), the edgewise pixel processor 32receives image data (N, 1), (FN, 2) to (FN, 63), and (N, 64) from thefilter calculator 31 in accordance with effective data-indicating signal“SE”.

[0263] As seen from FIG. 10(d), the edgewise pixel processor 32 feedsrequired image data (N, 1), (FN, 2) to (FN, 63) among the entered imagedata (N, 1), (FN, 2) to (FN, 63), and (N, 64) into the data write unit121 in accordance with mode information “M” from the register 33.

[0264] As seen from FIG. 10(d), the edgewise pixel processor 32prohibits feeding unnecessary image data (N, 64) in accordance with modeinformation “M”.

[0265] Image data (FN, 2) to (FN, 63) among required image data (N, 1),(FN, 2) to (FN, 63) are filtered image data.

[0266] As shown in FIG. 10(e), the edgewise pixel processor 32 feedswrite-indicating signal “SW”, as well as the required image data (N, 1),(FN, 2) to (FN, 63), into the data write unit 121.

[0267] The data write unit 121 writes required image data (N, 1), (FN,2) to (FN, 63) in sequence to the destination memory 11 in accordancewith write-indicating signal “SW” from the edgewise pixel processor 32.

[0268] The data write unit 121 writes the above image data when thewrite-indicating signal “SW” is at the level of “H (high)”.

[0269] Referring to FIG. 8(a), as a result of the above edgewise pixelprocessing, only the required image data (N, 1), (FN, 2) to (FN, 63),not the unnecessary image data (N, 64), are written to the destinationmemory 11.

[0270] Image data (N, 1), (FN, 2) to (FN, 63) written to the destinationmemory 11 are transmitted to the image memory 2.

[0271] The second filtering is now discussed with reference to FIG. 1,FIG. 8(b), FIG. 9, and FIGS. 11(a) to 11(e).

[0272] Steps taken until the filter calculator 31 of FIG. 9 feedsfiltered image data D# and effective data-indicating signal “SE” are thesame as the steps (see FIGS. 6(a) to 6(c)) taken until the filtercalculator 31 of FIG. 4 according to the previous embodiment feedsfiltered image data D# and effective data-indicating signal “SE”.Therefore, descriptions related to the above steps are omitted.

[0273] However, before starting the second filtering, mode signal “SM”sets mode information “M” into the register 33 of FIG. 9. Modeinformation “M” prohibits feeding rightmost and leftmost pieces of imagedata. Details of this step are discussed later.

[0274] As illustrated in FIG. 11(b), the edgewise pixel processor 32receives image data (N, 63), (FN, 64) to (FN, 125), and (N, 126) fromthe filter calculator 31 in accordance with effective data-indicatingsignal “SE”.

[0275] As seen from FIG. 11(d), the edgewise pixel processor 32 feedsrequired image data (FN, 64) to (FN, 125) among the entered image data(N, 63), (FN, 64) to (FN, 125), and (N, 126) into the data write unit121 in accordance with mode information “M” from the register 33. Thesecond filtering differs in mode information “M” from the firstfiltering.

[0276] As seen from FIG. 11(d), the edgewise pixel processor 32prohibits feeding unnecessary image data (N, 63) and (N, 126) inaccordance with mode information

[0277] The required image data (FN, 64) to (FN, 125) are filtered imagedata.

[0278] As shown in FIG. 11(e), the edgewise pixel processor 32 feedswrite-indicating signal “SW”, as well as the required image data (FN,64) to (FN, 125), into the data write unit 121.

[0279] The data write unit 121 writes the required image data (FN, 64)to (FN, 125) in sequence to the destination memory 11 in accordance withwrite-indicating signal “SW” from the edgewise pixel processor 32.

[0280] Referring to FIG. 8(b), as a result of the above edgewise pixelprocessing, the only the required image data (FN, 64) to (FN, 125), notthe unnecessary image data (N, 63) and (N, 126), are written to thedestination memory 11.

[0281] The image data (FN, 64) to (FN, 125) written to the destinationmemory 11 are transmitted to the image memory 2.

[0282] The third filtering is now discussed with reference to FIG. 1,FIG. 8(c), FIG. 9, and FIGS. 12(a) to 12(e).

[0283] Steps taken until the filter calculator 31 of FIG. 9 feedsfiltered image data D# and effective data-indicating signal “SE” are thesame as the steps (see FIGS. 7(a) to 7(c)) taken until the filtercalculator 31 of FIG. 4 according to the previous embodiment feedsfiltered image data D# and effective data-indicating signal “SE”.Therefore, descriptions related to the above steps are omitted.

[0284] However, mode signal “SM” sets mode information “M” into theregister 33 of FIG. 9 before the third filtering starts. Modeinformation “M” prohibits feeding a leftmost piece of image data.Details of this step are discussed later.

[0285] As illustrated in FIG. 12(b), the edgewise pixel processor 32receives image data (N, 125), (FN, 126) to (FN, 175), and (N, 176) fromthe filter calculator 31 in accordance with effective data-indicatingsignal “SE”.

[0286] As seen from FIG. 12(d), the edgewise pixel processor 32 feedsrequired image data (FN, 126) to (FN, 175), and (N, 176) among theentered image data (N, 125), (FN, 126) to (FN, 175), and (N, 176) inaccordance with mode information “M” from the register 33. The thirdfiltering differs in mode information “M” from the second filtering.

[0287] As seen from FIG. 12(d), the edgewise pixel processor 32 does notfeed unnecessary image data (N, 125) in accordance with mode information“M”.

[0288] The image data (FN, 126) to (FN, 175) among the required imagedata (FN, 126) to (FN, 175), and (N, 176) are filtered image data.

[0289] As shown in FIG. 12(e), the edgewise pixel processor 32 feedswrite-indicating signal “SW”, as well as the required image data (FN,126) to (FN, 175), and (N, 176), into the data write unit 121.

[0290] The data write unit 121 writes the required image data (FN, 126)to (FN, 175), (N, 176) in sequence to the destination memory 11 inaccordance with write-indicating signal “SW” from the edgewise pixelprocessor 32.

[0291] Referring to FIG. 8(c), as a result of the above edgewise pixelprocessing, only the required image data (FN, 126) to (FN, 175), (N,176), not the unnecessary image data (N, 125), are written to thedestination memory 11.

[0292] The image data (FN, 126) to (FN, 175), and (N, 176) written tothe destination memory 11 are transmitted to the image memory 2.

[0293] As a result, the image memory 2 of FIG. 1 stores line data thatconsist of image data (N, 1), (FN, 2) to (FN, 175), and (N, 176).

[0294] In this way, an image output circuit (not shown) feeds asuccessively created series of line data into a display device (notshown) from the image memory 2, thereby displaying the line data on thedisplay device (not shown).

[0295] The following discusses mode information “M” as illustrated inFIG. 9.

[0296] As shown in FIG. 9, the register 33 retains mode information “M”according to the entered mode signal “SM”.

[0297] Mode information “M” is free to change according to mode signal“SM”.

[0298] In the present embodiment, mode information “M” is set before thefirst filtering to process edgewise pixels during the first filtering.

[0299] Mode information “M” is again set after the first filtering toprocess the edgewise pixels during the second filtering.

[0300] Mode information “M” is again set after the second filtering toprocess edgewise pixels during the third filtering.

[0301] Mode signal “SM” is sent out by, e.g., a command from theprocessor 1.

[0302] Details on mode information “M” of FIG. 9 are now discussed.

[0303] FIGS. 13(a) to 13(d) are descriptive illustrations showing modeinformation “M” settable in the register 33 of FIG. 9. FIG. 13(a) is adescriptive illustration showing mode information “M” of mode 2′b 00.FIG. 13(b) is a descriptive illustration showing mode information “M” ofmode 2′b 01. FIG. 13(c) is a descriptive illustration showing modeinformation “M” of mode 2′b 10. FIG. 13(d) is a descriptive illustrationshowing mode information “M” of mode 2′b 11.

[0304] FIGS. 13(a), 13(b), 13(c), and 13(d) illustrate the filteringusing three-pixels-by-six-pixels image data 1 to 18 that are stored inthe source memory 10 of FIG. 1.

[0305] The filter calculator 31 of FIG. 9 feeds image data 2, 5, 8, 11,14, and 17 into the edgewise pixel processor 32.

[0306] Mode 2′b 00 is now discussed with reference to FIG. 13(a). Mode2′b 00 shows that rightmost and leftmost pieces of image data 2, 17among image data 2, 5, 8, 11, 14, and 17 from the filter calculator 31are non-filtered image data required for display; and the remainingimage data 5, 8, 11, and 14 are filtered image data.

[0307] When mode signal “SM” sets mode information “M” of mode 2′b 00into the register 33, then the edgewise pixel processor 32 feeds all ofthe entered image data 2, 5, 8, 11, 14, and 17 as well aswrite-indicating signal “SW”. The write-indicating signal “SW” writesall of the entered image data 2, 5, 8, 11, 14, and 17 to the destinationmemory 11.

[0308]FIG. 13(a) to FIG. 13(c) name the non-filtered image data requiredfor display as “through-data”.

[0309] Mode 2′b 00 is set when 3-lines-by-176-pixels image data istransmitted to the source memory 10 to filter target image data subjectto filtering, provided that a QCIF image is to be processed, and furtherthat each gang of three pixels-by-three pixels is to be filtered.

[0310] Mode 2′b 01 is now discussed with reference to FIG. 13(b). Mode2′b 01 shows that image data 2 among image data 2, 5, 8, 11, 14, and 17from the filter calculator 31 is non-filtered image data required fordisplay; image data 5, 8, 11, and 14 are filtered image data; and theremaining image data 17 is unnecessary image data.

[0311] When mode signal “SM” sets mode information “M” of mode 2′b 01into the register 33, then the edgewise pixel processor 32 feeds imagedata 2, 5, 8, 11, and 14 among the entered image data 2, 5, 8, 11, 14,and 17, but does not feed image data 17.

[0312] The edgewise pixel processor 32 feeds write-indicating signal“SW” to the data write unit 121. The write-indicating signal “SW” allowsthe data write unit 121 to write only image data 2, 5, 8, 11, and 14 tothe destination memory 11.

[0313] Mode 2′b 01 is set when, e.g., a rightmost piece of image data(N, 64) is not fed as illustrated in FIG. 10(d).

[0314] As a result, the register 33 is set into mode 2′b 01 during thefirst filtering.

[0315] Mode 2′b 10 is now discussed with reference to FIG. 13(c). Mode2′b 10 shows that image data 2 among image data 2, 5, 8, 11, 14, and 17from the filter calculator 31 is unnecessary image data; image data 5,8, 11, and 14 are filtered image data; and the remaining image data 17is non-filtered image data required for display.

[0316] When mode signal “SM” sets mode information “M” of mode 2′b 10into the register 33, then the edgewise pixel processor 32 feeds imagedata 5, 8, 11, 14, and 17 among image data 2, 5, 8, 11, 14, and 17, butdoes not feed image data 2.

[0317] The edgewise pixel processor 32 feeds write-indicating signal“SW” to the data write unit 121. The write-indicating signal “SW” allowsthe data write unit 121 to write only image data 5, 8, 11, 14, and 17 tothe destination memory 11.

[0318] Mode 2′b 10 is set when, e.g., a leftmost piece of image data (N,125) is not fed as illustrated in FIG. 12(d).

[0319] As a result, the register 33 is set into mode 2′b 10 during thethird filtering.

[0320] Mode 2′b 11 is now discussed with reference to FIG. 13(d). Mode2′b 11 shows that image data 2, 17 among image data 2, 5, 8, 11, 14, and17 from the filter calculator 31 are unnecessary image data; and imagedata 5, 8, 11, and 14 are filtered image data,

[0321] When mode signal “SM” sets mode information “M” of mode 2′b 11into the register 33, then the edgewise pixel processor 32 feeds imagedata 5, 8, 11, and 14 among image data 2, 5, 8, 11, 14, and 17, but doesnot feed image data 2 and 17.

[0322] The edgewise pixel processor 32 feeds write-indicating signal“SW” to the data write unit 121. The write-indicating signal “SW” allowsthe data write unit 121 to write only image data 5, 8, 11, and 14 to thedestination memory 11.

[0323] Mode 2′b 11 is set when, e.g., rightmost and leftmost pieces ofimage data (N, 63), (N, 126) are not fed as illustrated in FIG. 11(d).

[0324] As a result, the register 33 is set into mode 2′b 11 during thesecond filtering.

[0325] The following discusses mode information “M” with reference to aspecific example.

[0326] FIGS. 14(a), 14(b), and 14(c) illustrate how mode information “M”is used. FIG. 14(a) illustrates the use of mode 2′b 01. FIG. 14(b)illustrates the use of mode 2′b 11. FIG. 14(c) illustrates the use ofmode 2′b 10.

[0327] FIGS. 14(a), 14(b), and 14(c) show, as an illustration, howthree-pixels-by-six-pixels image data are filtered.

[0328] As illustrated in FIGS. 14(a) to 14 (c), assume that the imagememory 2 of FIG. 1 stores image data 1 to 18.

[0329] As shown in FIG. 14(a), assume that image data 1 to 9 aretransmitted to the source memory 10 of FIG. 1.

[0330] At this time, the register 33 is set into mode 2′b 01. As aresult, the edgewise pixel processor 32 feeds only image data 2 and 5among the entered image data 2, 5, and 8 from the filter calculator 31.

[0331] As illustrated in FIG. 14(b), assume that image data 4 to 15 aretransmitted to the source memory 10.

[0332] At this time, the register 33 is set into mode 2′b 11. As aresult, the edgewise pixel processor 32 feeds only image data 8 and 11among the entered image data 5, 8, 11, and 14 from the filter calculator31.

[0333] As shown in FIG. 14(c), assume that image data 10 to 18 aretransmitted to the source memory 10.

[0334] At this time, the register 33 of FIG. 9 is set into mode 2′b 10.As a result, the edgewise pixel processor 32 feeds only image data 14and 17 among the entered image data 11, 14, and 17 from the filtercalculator 31.

[0335] As described above, the image processor according to the presentembodiment is possible to prepare line data in a reduced time because agang of filtered image data is free of unnecessary image data (N, 64),(N, 63), (N, 126), and (N, 125), as illustrated in FIG. 8. Theunnecessary image data (N, 64), (N, 63), (N, 126), and (N, 125) areproduced in the course of filtering the target image data subject tofiltering.

[0336] The image processor according to the present embodiment includesthe construction of the image processor according to the previousembodiment, and consequently provides beneficial effects similar tothose achieved in the previous embodiment.

[0337] (Third Embodiment)

[0338] An image processor according to a third embodiment includes afiltering circuit substituted for the filtering circuit 3 of FIG. 1. Thefiltering circuit 5 is discussed below. The image processor according tothe present embodiment is similar to those of the image processor ofFIG. 1 except for the filtering circuit as just discussed above.

[0339]FIG. 15 is a block diagram illustrating the filtering circuit 5.As shown in FIG. 15, the filtering circuit 5 includes a pixel-retainingbuffer unit 50, selectors 52, 53, and a selector controller 51, otherthan components of the filtering circuit 4 of FIG. 9.

[0340] Filtering is now discussed in brief.

[0341]FIG. 16 is a schematic illustration showing how the imageprocessor according to the present embodiment is operable to filtertarget image data subject to filtering. FIG. 16 is similar in notationto FIG. 2.

[0342] As illustrated in FIG. 16, three-pixels-by-five-pixels image data101 obtained by dividing 3-lines-by-176-pixels image data 100 istransmitted to the source memory 10 from the image memory 2 of FIG. 1.

[0343] The source memory 10 feeds the image data 101 in sequence to thefiltering circuit 5 for each piece of image data.

[0344] The filtering circuit 5 filters a piece of target image datasubject to filtering using the given three-pixels-by-three-pixels imagedata.

[0345] In this way, the filtering circuit 5 filters all three pieces oftarget image data subject to filtering that are stored in the image data101.

[0346] When completing the present filtering, then the filtering circuit5 places image data 109 into the pixel-retaining buffer unit 50 for useat the time of the next filtering.

[0347] Subsequently, three-pixels-by-four-pixels image data 106 obtainedby dividing 3-lines-by-176-pixels image data 100 is transmitted to thesource memory 10 from the image memory 2.

[0348] The filtering circuit 5 filters target image data subject tofiltering using the image data 106 in the source memory 10 and the imagedata 109 in the pixel-retaining buffer 50.

[0349] The above steps are repeated to filter all pieces of target imagedata subject to filtering that are stored in 3-lines-by-176-pixels imagedata 100. As a result, a line of filtered image data 105 is achieved.

[0350] As previously discussed, when filtering the image data 101 iscompleted, then the filtering circuit 5 according to the presentembodiment puts the image data 109 among the image data 101 into thepixel-retaining buffer unit 50 in order to use the image data 109 at thetime of the following filtering.

[0351] This feature provides a smaller number of times of transferringimage data from the image memory 2 to the source memory 10 and a smallernumber of times of transferring image data from the source memory 10 tothe filtering circuit 5.

[0352] The following discusses details of the filtering with referenceto FIGS. 1, 15, 17, and 18, in which the source memory 10 of FIG. 1 isadapted to store 3-lines-by-64-pixels image data at maximum.

[0353] Assume that each gang of three-pixels-by-three-pixels image datais filtered, and further that a pixel located at the center of threepixels-by-three pixels has target image data subject to filtering.

[0354] FIGS. 17(a), 17(b), and 17(c) are illustrations showing a flow offiltering steps. FIG. 17(a) is an illustration showing a flow of firstfiltering. FIG. 17(b) is an illustration showing a flow of secondfiltering. FIG. 17(c) is an illustration showing a flow of thirdfiltering. FIG. 17 illustrates the same reference numerals on componentssimilar to those described in FIG. 1.

[0355] FIGS. 18(a), 18(b), and 18(c) are time charts showingcharacteristics of the filtering according to the present embodiment.FIG. 18(a) is an illustration showing how image data is transferred froma shift register 30 to the pixel-retaining buffer unit 50 at the end ofthe first filtering. FIG. 18(b) is an illustration showing when thesecond filtering is started. FIG. 18(c) is an illustration showing imagedata written to a destination memory 11 from a data write unit 121.

[0356] The first filtering is similar to that according to the secondembodiment as illustrated in FIGS. 10(a) to 10(e). Therefore,descriptions related thereto are omitted.

[0357] However, the first filtering is followed by additional steps asdiscussed below when the first filtering is completed.

[0358] As illustrated in FIG. 18(a), at the last cycle “CY184” of thefirst filtering, flip-flops FF1 to FF9 of the shift register 30 feedsimage data (N−1, 62) to (N+1, 64), respectively.

[0359] Image data (N−1, 63), (N, 63) (N+1, 63), (N−1, 64), (N, 64), and(N+1, 64) among the above image data (N−1, 62) to (N+1, 64) are placedinto the pixel-retaining buffer unit 50 for use at the time of thesecond filtering.

[0360] More specifically, the pixel-retaining buffer unit 50 storesimage data (N−1, 63), (N, 63), (N+1, 63), (N−1, 64), (N, 64), and (N+1,64) that are supplied at the last cycle “CY184” from flip-flops FF4,FF5, FF6, FF7, FF8, and FF9, respectively.

[0361] The second filtering is now described. After the first filteringends, mode signal “SM” sets up mode information “M” (mode 2′b 11 of FIG.13(d)) that prohibits feeding rightmost and leftmost pieces of imagedata.

[0362] As illustrated in FIG. 17(b), image data (N−1, 65), (N, 65),(N+1, 65) to (N−1, 126), (N, 126), and (N+1, 126) are transmitted to thesource memory 10 from the image memory 2.

[0363] At this time, image data (N−1, 63), (N, 63), (N+1, 63), (N−1,64), (N, 64), and (N+1, 64) are not transmitted to the source memory 10.Instead, the second filtering employs image data (N−1, 63), (N, 63),(N+1, 63), (N−1, 64), (N, 64), and (N+1, 64), all of which are retainedin pixel-retaining buffer unit 50.

[0364] As shown in FIG. 18(b), at the first cycle “CY#1” of the secondfiltering, the flip-flop FF 9 feeds image data (N−1, 65) from the sourcememory 10.

[0365] At cycle “CY#1”, the flip-flops FF3, FF6 feed image data (N−1,63), (N−1, 64) from the pixel-retaining buffer unit 50, respectively.

[0366] At the following cycle “CY#2”, flip-flop FF 9 feeds image data(N, 65) from the source memory 10, while flip-flop FF 8 feeds image data(N−1, 65) that is shifted from flip-flop FF 9.

[0367] At cycle “CY#2”, flip-flops FF3, FF6 feeds image data (N, 63),(N, 64) from the pixel-retaining buffer unit 50, respectively, whileflip-flops FF2, FF5 feeds image data (N−1, 63), (N−1, 64) that areshifted from flip-flops FF3, FF6, respectively.

[0368] At the following cycle “CY#3”, flip-flop FF 9 feeds image data(N+1, 65) from the source memory 10, while flip-flops FF7, FF8 feedimage data (N−1, 65), (N, 65) that are shifted from flip-flops FF8, FF9,respectively.

[0369] At cycle “CY#3”, flip-flops FF3, FF6 feeds image data (N+1, 63),(N+1, 64) from the pixel-retaining buffer unit 50, respectively, whileflip-flops FF1, FF2, FF4, and FF5 feed image data (N−1, 63), (N, 63),(N−1, 64), and (N, 64) that are shifted from flip-flops FF2, FF3, FF5,and FF6, respectively.

[0370] At this time, as shown in FIG. 18(c), the first filtered imagedata (FN, 64) is fed. Thereafter, usual shift actions similar to thoseaccording to the second embodiment are provided to filter target imagedata subject to filtering.

[0371] Similar to the first filtering, image data for use at the time ofthe third filtering are held in the pixel-retaining buffer unit 50 atthe end of the second filtering.

[0372] More specifically, when the second filtering is terminated, thenthe pixel-retaining buffer unit 50 retains image data (N−1, 125), (N,125), (N+1, 125), (N−1, 126), (N, 126), and (N+1, 126) from flip-flopsFF4, FF5, FF6, FF7, FF8, and FF9, respectively.

[0373] The third filtering is now described. After the end of the secondfiltering, mode signal “SM” sets up mode information “M” (mode 2′b 10 ofFIG. 13(c)) that prohibits feeding a leftmost piece of image data.

[0374] As shown in FIG. 17(c), image data (N−1, 127), (N, 127), (N+1,127) to (N−1, 176), (N, 176), and (N+1, 176) are transmitted to thesource memory 10 from the image memory 2.

[0375] At this time, image data (N−1, 125), (N, 125), (N+1, 125), (N−1,126), (N, 126), and (N+1, 126) are not transmitted to the source memory10. Instead, the third filtering employs image data (N−1, 125), (N,125), (N+1, 125), (N−1, 126), (N, 126), and (N+1, 126) that are held inthe pixel-retaining buffer unit 50.

[0376] In the third filtering, first to third cycles are similar tothose in the second filtering. More specifically, the shift register 30feeds image data from the source memory 10 and the pixel-retainingbuffer unit 50 to filter target image data subject to filtering. Thefiltering at the fourth or greater cycles is similar to that accordingto the second embodiment.

[0377] The following discusses, with reference to FIG. 15, details ofimage data transfer to the pixel-retaining buffer unit 50 and details ofimage data transfer from the pixel-retaining buffer unit 50 to the shiftregister 30.

[0378] Mode information “M” currently held in the register 33 is sent tothe selector controller 51.

[0379] The selector controller 51 produces selection signal “SC” basedon mode information “M”. The selection signal SC is provided toselectors 52 and 53.

[0380] The selector 52 receives image data from the pixel-retainingbuffer unit 50 and image data from flip-flop FF 4.

[0381] The selector 52 selects either the image data from thepixel-retaining buffer unit 50 or that from flip-flop FF 4 in accordancewith selection signal “SC”. The selector 52 feeds the selected imagedata into flip-flop FF 3.

[0382] The selector 53 receives image data from the pixel-retainingbuffer unit 50 and image data from flip-flop FF 7.

[0383] The selector 53 selects either the image data from thepixel-retaining buffer unit 50 or that from flip-flop FF 7 in accordancewith selection signal “SC”. The selector 53 feeds the selected imagedata into the flip-flop FF 6.

[0384] The above steps are now described with reference to FIGS. 18(a)and 18(b). As illustrated in FIG. 18(a), at cycle “CY184” of the firstfiltering, image data (N−1, 63), (N, 63), (N+1, 63), (N−1, 64), (N, 64),and (N+1, 64) from flip-flops FF4, FF5, FF6, FF7, FF8, and FF9 are heldin the pixel-retaining buffer unit 50.

[0385] As shown in FIG. 18(b), at cycle “CY#1” of the second filtering,flip-flops FF3, FF6 feed image data (N−1, 63), (N−1, 64), respectively.

[0386] The selector 52 selects image data (N−1, 63) from thepixel-retaining buffer unit 50 before cycle “CY#1” in accordance withselection signal “SC”, and then feeds the selected image data (N−1, 63)into flip-flop FF 3.

[0387] The selector 53 selects image data (N−1, 64) from thepixel-retaining buffer unit 50 before cycle “CY#1” in accordance withselection signal “SC”, and then feeds the selected image data (N−1, 64)into flip-flop FF 6.

[0388] As shown in FIG. 18(b), at cycle “CY#2”, flip-flops FF3, FF6 feedimage data (N, 63), (N, 64), respectively.

[0389] The selector 52 selects image data (N, 63) from thepixel-retaining buffer unit 50 before cycle “CY#2” in accordance withselection signal “SC”, and then feeds the selected image data (N, 63)into flip-flop FF 3.

[0390] The selector 53 selects image data (N, 64) from thepixel-retaining buffer unit 50 before cycle “CY#2” in accordance withselection signal “SC”, and then feeds the selected image data (N, 64)into flip-flop FF 6.

[0391] As illustrated in FIG. 18(b), at cycle “CY#3”, flip-flops FF3,FF6 feeds image data (N+1, 63), (N+1, 64), respectively.

[0392] The selector 52 selects image data (N+1, 63) from thepixel-retaining buffer unit 50 before cycle “CY#3” in accordance withselection signal “SC”, and then feeds the selected image data (N+1, 63)into flip-flop FF 3.

[0393] The selector 53 selects image data (N+1, 64) from thepixel-retaining buffer unit 50 before cycle “CY#3” in accordance withselection signal “SC”, and then feeds the selected image data (N+1, 64)into flip-flop FF 6.

[0394] Thereafter, the selectors 52, 53 select, in accordance withselection signal “SC”, respective pieces of image data that flip-flopsFF4, FF7 feed.

[0395] As previously discussed, the image processor according thepresent embodiment is operable to retain image data required for use atthe time of the next filtering when the present filtering is terminated.As a result, the retained image data are usable at the time of the nextfiltering. This feature provides a reduced number of times oftransferring the data.

[0396] The image processor according to the present embodiment includesthe construction of the image processor according to the secondembodiment. Therefore, the image processor according to the presentembodiment provides beneficial effects similar to those obtained in thesecond embodiment.

[0397] (Fourth Embodiment)

[0398] An image processor according to a fourth embodiment includes afiltering circuit 6 substituted for the filtering circuit 3 of FIG. 1.The filtering circuit 6 is discussed below. The image processoraccording to the present embodiment is similar in construction to theimage processor of FIG. 1 except for filtering circuit as just discussedabove.

[0399]FIG. 19 is a block diagram illustrating the filtering circuit 6.FIG. 19 illustrates the same reference characters on components similarto those described in FIG. 9.

[0400] As illustrated in FIG. 19, the filtering circuit 6 includes adata output control unit 81 that is substituted for the data outputcontrol unit 80 of FIG. 9.

[0401] The data output control unit 81 includes a down counter 62, acoincidence detector 61, and an edgewise pixel processor 32.

[0402] Pixel number-setting signal “SN” enters the down counter 62 andcoincidence detector 61 in response to, e.g., instructions from theprocessor 1 before the filtering starts. As a result, the number ofpixels for one line is set as initial value in the down counter 62 andcoincidence detector 61.

[0403] The down counter 62 counts down each time when the edgewise pixelprocessor 32 feeds image data D$.

[0404] More specifically, the down counter 62 provides a countdown eachtime when the edgewise pixel processor 32 feeds write-indicating signal“SW” having a “H”-level into the down counter 62.

[0405] The down counter 62 feeds countdown signal “SD” into thecoincidence detector 61. Countdown signal “SD” shows the number ofcount.

[0406] The coincidence detector 61 compares the number of pixels, set upby pixel number-setting signal “SN”, with the number of count that isexpressed by countdown signal “SD”. When the number of pixels iscoincident with the number of count, then the coincidence detector 61feeds coincidence signal “SA” having a “H”-level into the edgewise pixelprocessor 32.

[0407] The coincidence detector 61 feeds coincidence signal “SA” having“H”-level into the edgewise pixel processor 32 when countdown signal“SD” names the number of count as “1”.

[0408] As a result, coincidence signal “SA” having “H”-level is sent outonly before the first and last image data “D$” are fed from the edgewisepixel processor 32.

[0409] The edgewise pixel processor 32 feeds the entered image data whencoincidence signal “SA” having “H”-level enters the edgewise pixelprocessor 32, when coincidence signal “SA” having “L”-level, notfiltering start signal “Ss”, enters the edgewise pixel processor 32, andwhen coincidence signal “SA” having “L”-level, not filtering end signal“Se”, enters the edgewise pixel processor 32.

[0410] The edgewise pixel processor 32 does not feed the entered imagedata when coincidence signal “SA” having “L”-level as well as filteringstart signal “Ss” enters the edgewise pixel processor 32, and whencoincidence signal “SA” having “L”-level as well as filtering end signal“Se” enters the edgewise pixel processor 32. Specific examples of theabove are discussed later.

[0411] The edgewise pixel processor 32 feeds a write-indicating signalhaving “H”-level when coincidence signal “SA” having “H”-level entersthe edgewise pixel processor 32, when coincidence signal “SA” having“L”-level, not filtering start signal “Ss”, enters the edgewise pixelprocessor 32, and when coincidence signal “SA” having “L”-level, notfiltering end signal “Se”, enters the edgewise pixel processor 32.

[0412] The edgewise pixel processor 32 does not feed thewrite-indicating signal having “H”-level when coincidence signal “SA”having “L”-level as well as filtering start signal “Ss” enters theedgewise pixel processor 32, and when coincidence signal “SA” having“L”-level as well as filtering end signal “Se” enters the edgewise pixelprocessor 32. Specific examples of the above are discussed later.

[0413] Features of the filtering according to the present embodiment arenow described in brief.

[0414]FIG. 20 is a schematic illustration showing how the imageprocessor according to the present embodiment is operable to filtertarget image data subject to filtering.

[0415]FIG. 20 is similar in notation to FIG. 2.

[0416] As illustrated in FIG. 20, pursuant to the present embodiment,176-pixels of one line are set in the down counter 62.

[0417] The down counter 62 counts downward by “1” every time when theedgewise pixel processor 32 feeds image data “D$”.

[0418] The data output control unit 81 feeds only required image data“$” among the entered image data in accordance with information from thedown counter 62.

[0419] In this way, the edgewise pixel-processing of3-lines-by-176-pixels image data is achievable only by at first settingthe number of pixels for one line into the down counter 62.

[0420] According to the second embodiment, mode information M is set upthree times in order to perform the edgewise pixel-processing of3-lines-by-176-pixels image data.

[0421] Details of the filtering are now discussed.

[0422] The following description presupposes that the source memory 10of FIG. 1 is possible to store 3-lines-by-64-pixels image data atmaximum.

[0423] Each gang of three-pixels-by-three-pixels image data is filtered.A pixel located at the center of three pixels-by-three pixels has targetimage data subject to filtering.

[0424] FIGS. 21(a), 21(b), and 21(c) are illustrations showing a flow offiltering steps. FIG. 21(a) is an illustration showing a flow of thefirst filtering. FIG. 21(b) is an illustration showing a flow of thesecond filtering. FIG. 21(c) is an illustration showing a flow of thethird filtering.

[0425] FIGS. 21(a), 21(b), and 21(c) provide the same referencecharacters on components similar to those described in FIG. 1.

[0426] FIGS. 22(a), 22(b), 22(c), 22(d), 22(e), and 22(f) are timecharts illustrating the first filtering. FIG. 22(a) is an illustrationshowing, for each cycle, image data sent to the filter calculator 31 ofFIG. 19. FIG. 22(b) is an illustration showing the number of countprovided by the down counter 62. FIG. 22(c) is an illustration showingimage data fed from the filter calculator 31. FIG. 22(d) is anillustration showing an effective data-indicating signal from the filtercalculator 31. FIG. 22(e) is an illustration showing image data writtenby a data write unit 121 to a destination memory 11. FIG. 22(f) is anillustration showing a write-indicating signal fed from the edgewisepixel processor 32.

[0427] FIGS. 23(a), 23(b), 23(c), 23(d), 23(e), and 23(f) are timecharts illustrating the second filtering. FIG. 23(a) is an illustrationshowing, for each cycle, image data sent to the filter calculator 31.FIG. 23(b) is an illustration showing the number of count provided bythe down counter 62. FIG. 23(c) is an illustration showing image datafed from the filter calculator 31. FIG. 23(d) is an illustration showingan effective data-indicating signal from the filter calculator 31. FIG.23(e) is an illustration showing image data written by the data writeunit 121 to the destination memory 11. FIG. 23(f) is an illustrationshowing a write-indicating signal from the edgewise pixel processor 32.

[0428] FIGS. 24(a), 24(b), 24(c), 24(d), 24(e), and 24(f) are timecharts illustrating the third filtering. FIG. 24(a) is an illustrationshowing, for each cycle, image data sent to the filter calculator 31.FIG. 24(b) is an illustration showing the number of count provided bythe down counter 62. FIG. 24(c) is an illustration showing image datafed from the filter calculator 31. FIG. 24(d) is an illustration showingan effective data-indicating signal from the filter calculator 31. FIG.24(e) is an illustration showing image data written by the data writeunit 121 to the destination memory 11. FIG. 24(f) is an illustrationshowing a write-indicating signal from the edgewise pixel processor 32.

[0429] The first filtering is now described with reference to FIG. 1,FIG. 19, FIG. 21(a), and FIGS. 22(a) to 22(f).

[0430] Steps taken until the filter calculator 31 feeds filtered imagedata “D#” and effective data-indicating signal “SE” are the same asthose (see FIG. 5(a) to 5(c)) taken until the filter calculator 31 ofFIG. 4 according to the first embodiment feeds filtered image data “D#”and effective data-indicating signal “SE”.

[0431] As illustrated in FIG. 19, pixel number-setting signal “SN” sets“176”-pixels for one line into the down counter 62 and the coincidencedetector 61 before the first filtering.

[0432] As shown in FIG. 22(b), the down counter 62 initially feedscountdown signal “SD” to the coincidence detector 61. Countdown signal“SD” expresses the number of count, “176”.

[0433] At this time, the number of pixels, “176”, set up by pixelnumber-setting signal “SN” is coincident with the number of count,“176”, expressed by countdown signal “SD”. As a result, the coincidencedetector 61 feeds coincidence signal “SA” having “H”-level into theedgewise pixel processor 32.

[0434] As shown in FIG. 22(e) and 22(f), the edgewise pixel processor 32in receipt of coincidence signal “SA” feeds image data (N, 1) from thefilter calculator 31 and write-indicating signal “SW” having “H”-level.

[0435] The edgewise pixel processor 32 feeds write-indicating signal“SW” having “H”-level into the down counter 62.

[0436] The down counter 62 counts down by one from initial value “176”.As illustrated in FIG. 22(b), the down counter 62 feeds countdown signal“SD” representative of the number of count, “175”, into the coincidencedetector 61.

[0437] At this time, the number of pixels, “176”, set up by pixelnumber-setting signal “SN” does not coincide with the number of count,“175”, expressed by countdown signal “SD”. As a result, the coincidencedetector 61 feeds coincidence signal “SA” having “L”-level.

[0438] As shown in FIG. 22(e) and 22(f), the edgewise pixel processor 32feeds filtered image data (FN, 2) from the filter calculator 31 andwrite-indicating signal “SW” having “H”-level.

[0439] As illustrated in FIG. 22(f), the edgewise pixel processor 32feeds write-indicating signal “SW” having “H”-level into the downcounter 62.

[0440] Thereafter, the coincidence detector 61 continues to feedcoincidence signal “SA” having “L”-level. As illustrated in FIG. 22(e),the edgewise pixel processor 32 feeds filtered image data (FN, 3) to(FN, 63) from the filter calculator 31 into the data write unit 121.

[0441] As illustrated in FIG. 22(f), the edgewise pixel processor 32feeds write-indicating signal “SW” having “H”-level into the data writeunit 121 while feeding the filtered image data (FN, 3) to (FN, 63) intothe data write unit 121.

[0442] A data readout unit 120 feeds filtering end signal “Se” into theedgewise pixel processor 32 after the edgewise pixel processor 32 feedsfiltered image data (FN, 63) into the data write unit 121.

[0443] As illustrated in FIG. 22(e), the edgewise pixel processor 32 inreceipt of filtering end signal “Se” and coincidence signal “SA” having“L”-level does not feed the last image data (N, 64) from the filtercalculator 31.

[0444] As illustrated in FIG. 22(f), the edgewise pixel processor 32 inreceipt of filtering end signal “Se” and coincidence signal “SA” having“L”-level does not feed write-indicating signal “SW” having “H”-level.

[0445] As a result, the down counter 62 does not count down, and thenumber of count at the end of the first filtering is “113”.

[0446] Consequently, as illustrated in FIG. 21(a), only the requiredimage data (N, 1), (FN, 2) to (FN, 63), not the unnecessary image data(N, 64), are written to the destination memory 11.

[0447] The image data (N, 1), (FN, 2) to (FN, 63) written to thedestination memory 11 are transferred to the image memory 2.

[0448] The second filtering is now discussed with reference to FIG. 1,FIG. 19, FIG. 21(b), and FIG. 23(a) to 23(f).

[0449] Steps taken until the filter calculator 31 feeds filtered imagedata “D#” and effective data-indicating signal “SE” are the same asthose (see FIG. 6(a) to 6(c)) taken until the filter calculator 31 ofFIG. 4 according to the first embodiment feeds filtered image data “D#”and effective data-indicating signal “SE”. Therefore, descriptionsrelated thereto are omitted.

[0450] As illustrated in FIGS. 23(c) and 23(d), the edgewise pixelprocessor 32 receives image data (N, 63), (FN, 64) to (FN, 125), and (N,126) from the filter calculator 31 in accordance with effectivedata-indicating signal “SE”.

[0451] At this time, the number of pixels, “176”, set up by the pixelnumber-setting signal “SN” as illustrated in FIG. 23(b) does notcoincide with the number of count shown by countdown signal “SD”. Thecoincidence detector 61 feeds coincidence signal “SA” having “L”-levelinto the edgewise pixel processor 32.

[0452] In order to start the second filtering, the data readout unit 120feeds filtering start signal “Ss” into the edgewise pixel processor 32.

[0453] As shown in FIG. 23(e), the edgewise pixel processor 32 inreceipt of filtering start signal “Ss” and coincidence signal “SA”having “L”-level does not feed image data (N, 63) that is initially fedfrom the filter calculator 31 into the edgewise pixel processor 32.

[0454] As shown in FIG. 23(f), the edgewise pixel processor 32 inreceipt of filtering start signal “Ss” and coincidence signal “SA”having “L”-level does not feed write-indicating signal “SW” having“H”-level.

[0455] As a result, the down counter 62 performs no countdown. At thistime, the number of count is still “113”, as shown in FIG. 23(b).

[0456] Thereafter, coincidence signal “SA” having “L”-level, notfiltering start signal “Ss”, enters the edgewise pixel processor 32. Asillustrated in FIG. 23(e), the edgewise pixel processor 32 feedsfiltered image data (FN, 64) to (FN, 125) from the filter calculator 31.

[0457] As shown in FIG. 23(f), the edgewise pixel processor 32 feedswrite-indicating signal “SW” having “H”-level to the data write unit 121while feeding the filtered image data (FN, 64) to (FN, 125) into thedata write unit 121.

[0458] The data readout unit 120 feeds filtering end signal “Se” intothe edgewise pixel processor 32 after the edgewise pixel processor 32feeds the filtered image data (FN, 125), as shown in FIG. 23(e).

[0459] As illustrated in FIG. 23(e), the edgewise pixel processor 32 inreceipt of filtering end signal “Se” and coincidence signal “SA” having“L”-level does not feed image data (N, 126) that is the last image datafed from the filter calculator 31.

[0460] As illustrated in FIG. 23(f), the edgewise pixel processor 32 inreceipt of filtering end signal “Se” and coincidence signal “SA” having“L”-level does not feed write-indicating signal “SW” having “H”-level.

[0461] As a result, the down counter 62 performs no countdown, and thenumber of count at the end of the second filtering is “51”.

[0462] Consequently, as illustrated in FIG. 21(b), only the requiredimage data (FN, 64) to (FN, 125), not the unnecessary image data (N, 63)and (N, 126), are written to the destination memory 11,

[0463] The image data (FN, 64) to (FN, 125) written to the destinationmemory 11 are transmitted to the image memory 2.

[0464] The third filtering is now discussed with reference to FIG. 1,FIG. 19, FIG. 21(c), and FIG. 24(a) to 24(f).

[0465] Steps taken until the filter calculator 31 feeds filtered imagedata “D#” and effective data-indicating signal “SE” are the same asthose (see FIG. 7(a) to 7(c)) taken until the filter calculator 31 ofFIG. 4 according to the first embodiment feeds filtered image data “D#”and effective data-indicating signal “SE”. Therefore, descriptionsrelated thereto are omitted.

[0466] As illustrated in FIGS. 24(c) and 24(d), the edgewise pixelprocessor 32 receives image data (N, 125), (FN, 126) to (FN, 175), and(N, 176) from the filter calculator 31 in accordance with effectivedata-indicating signal “SE”.

[0467] At this time, the number of pixels, “176”, set up by the pixelnumber-setting signal “SN” as illustrated in FIG. 24(b) does notcoincide with the number of count shown by countdown signal “SD”. Thecoincidence detector 61 feeds coincidence signal “SA” having “L”-levelto the edgewise pixel processor 32.

[0468] In order to start the third filtering, the data readout unit 120feeds filtering start signal “Ss” to the edgewise pixel processor 32.

[0469] As shown in FIG. 24(e), the edgewise pixel processor 32 inreceipt of filtering start signal “Ss” and coincidence signal “SA”having “L”-level does not feed image data (N, 125) that is the firstimage data fed into the edgewise pixel processor 32 from the filtercalculator 31.

[0470] As shown in FIG. 24(f), the edgewise pixel processor 32 inreceipt of filtering start signal “Ss” and coincidence signal “SA”having “L”-level does not feed write-indicating signal “SW” having“H”-level.

[0471] As a result, the down counter 62 performs no countdown. At thistime, the number of count is still “51”, as shown in FIG. 24(b).

[0472] Thereafter, coincidence signal “SA” having “L”-level, notfiltering start signal “Ss”, enters the edgewise pixel processor 32. Asillustrated in FIG. 24(e), the edgewise pixel processor 32 feedsfiltered image data (FN, 126) to (FN, 175) from the filter calculator31.

[0473] As shown in FIG. 24(f), the edgewise pixel processor 32 feedswrite-indicating signal “SW” having “H”-level to the data write unit 121while feeding the filtered image data (FN, 126) to (FN, 175) into thedata write unit 121.

[0474] The down counter 62 provides the number of count, “1”, after theedgewise pixel processor 32 feeds filtered image data (FN, 175), asshown in FIG. 24(b).

[0475] As a result, countdown signal “SD” representative of the numberof count, “1”, enters the coincidence detector 61. The coincidencedetector 61 feeds coincidence signal “SA” having “H”-level to theedgewise pixel processor 32.

[0476] As illustrated in FIG. 24(e), the edgewise pixel processor 32 inreceipt of coincidence signal “SA” having “H”-level feeds image data (N,126) that is the last image data coming from the filter calculator 31 tothe edgewise pixel processor 32.

[0477] As illustrated in FIG. 24(f), the edgewise pixel processor 32 inreceipt of coincidence signal “SA” having “H”-level feedswrite-indicating signal “SW” having “H”-level.

[0478] Consequently, as illustrated in FIG. 21(c), only the requiredimage data (FN, 126) to (FN, 175), and (N, 176), not the unnecessaryimage data (N, 125), are written to the destination memory 11.

[0479] The image data (FN, 126) to (FN, 175), and (N, 176) written tothe destination memory 11 are transmitted to the image memory 2.

[0480] As described above, the image processor according to the presentembodiment is possible to prepare line data in a reduced time because agang of filtered image data is free of unnecessary image data (N, 64),(N, 63), (N, 126), and (N, 125), which are produced in the course offiltering the target image data subject to filtering.

[0481] The image processor according to the present embodiment initiallysets up the number of pixels to be filtered. Such a simple setupprovides subsequent edgewise pixel processing. This feature make itfeasible to set up edgewise pixel-processing information at a smallernumber of times.

[0482] The image processor according to the present embodiment includesthe construction of that according to the first embodiment. Therefore,the image processor according to the present embodiment providesbeneficial effects similar to those obtained in the first embodiment.

[0483] Having described preferred embodiments of the invention withreference to the accompanying drawings, it is to be understood that theinvention is not limited to those precise embodiments, and that variouschanges and modifications may be effected therein by one skilled in theart without departing from the scope or spirit of the invention asdefined in the appended claims.

What is claimed is:
 1. An image-processing method comprising:transferring image data to a storage unit, the image data being formedby several pieces of image data, the image data being separated fromseveral lines of image data; sequentially reading out the several piecesof image data from said storage unit; and filtering target image datasubject to filtering using predetermined pieces of the read image data.2. An image-processing method comprising: sequentially entering severalpieces of image data that are used to filter several pieces of targetimage data subject to filtering; shifting the sequentially enteredseveral pieces of image data; parallel-feeding predetermined pieces ofthe shifted image data; and filtering the several pieces of target imagedata subject to filtering using the parallel-fed predetermined pieces ofthe shifted image data.
 3. An image processor comprising: a firststorage unit operable to store image data formed by several pieces ofimage data, the image data being separated from several lines of imagedata; a data readout unit operable to sequentially read out the severalpieces of image data stored by said first storage unit; a filtering unitoperable to filter target image data subject to filtering usingpredetermined pieces of the image data that are read out from said datareadout unit; a second storage unit operable to store the filteredtarget image data subject to filtering; and a data write unit operableto write the filtered target image data subject to filtering to saidsecond storage unit.
 4. An image processor as defined in claim 3,wherein said filtering unit comprises a data output control unitoperable to feed the filtered target image data subject to filtering,but operable not to feed a predetermined piece of non-filtered imagedata in accordance with mode information.
 5. An image processor asdefined in claim 3, wherein said filtering unit comprises a data outputcontrol unit operable to provide a countdown from an initial value eachtime when the image data is fed, the initial value being determined inaccordance with the number of pixels to be processed, said data outputcontrol unit being operable to feed only a predetermined piece ofnon-filtered image data as well as filtered target image data subject tofiltering in accordance with results from the countdown.
 6. An imageprocessor as defined in claim 3, wherein said filtering unit comprises aimage data-retaining unit operable to retain several pieces of imagedata for use at the time of next filtering, the several pieces of imagedata for use at the time of next filtering being selected from among theseveral pieces of image data read out by said data readout unit fromsaid first storage unit.